1. Field of the Invention
This invention relates generally to semiconductor processes for forming transistors and, more specifically, to processes for forming trench contacts and local interconnects to a replacement gate structure on a semiconductor substrate.
2. Description of the Related Art
Transistors such as planar transistors have been the core of integrated circuits for several decades. During the use of transistors, the size of the individual transistors has steadily decreased through advances in process development and the need to increase feature density. Current scaling employs 32 nm technologies with development also progressing towards 20 nm and beyond technologies (e.g., 15 nm technologies).
Replacement gate processes (flows) are becoming more commonly utilized as they avoid certain problems found in gate first processes. For example, replacement gate processes may avoid problems associated with the stability of the work function material used in the gates. Replacement gate processes, however, may require the insertion of new process modules such as CMP (chemical mechanical polishing).
Additionally, most replacement gate processes suffer from alignment issues when making trench contacts and/or local interconnect connections to the gate. For example, most replacement gate processes are not self-aligned and can easily fail from misalignment during processing. It may also be difficult to pattern bidirectional local interconnect and/or reduce the number of interface layers from the local interconnect to either the gate or the source/drain of the gate.
To solve some of these issues, process flows have been made that attempt to create a self-aligned trench contact that extends above the gate to allow less complex local interconnect flow. Such process flows, however, are typically very complex, have many resistive interfaces, and have high manufacturing costs due to the complex process flow. Additionally, there is a low manufacturing margin for misalignments or other errors due to the complexity of the processes as these processes may have severely restrictive design and/or alignment rules.
FIG. 1 depicts an embodiment of prior art transistor 50 with replacement gate structure 52 on semiconductor substrate 54. Replacement gate structure 52 includes gates 56 surrounded by gate spacers 58. Source/drains 60 may be located in well region 62 of substrate 54. In addition, one or more gates may be located above isolation region 64 of substrate 54.
Trench contacts 66 are used to contact source/drains 60 to local interconnects 68A. Local interconnects 68A may be merged with local interconnect 68B to provide routing to local interconnect 68C, which is connected to gate 56′.
As can be seen in FIG. 1, any misalignment in trench contacts 66 may easily cause shorting to gates 56. Thus, there must be restrictive design/alignment rules to inhibit shorts between trench contacts 66 and gates 56. In addition, there may easily be alignment issues between local interconnect 68C and gate 56′ without restrictive alignment rules.
Also, as seen in FIG. 1, routing between local interconnects 68A, 68B, 68C can be complex and involve many process steps. The numerous process steps may increase the likelihood of resistive interfaces forming between the local interconnects and/or alignment issues between the local interconnects.
Thus, there is a need for a method to self-align trench contacts to the sources/drains and extend the trench contacts above the gates.